The formation of various integrated circuit (IC) structures on a wafer often relies on lithographic processes, sometimes referred to as photolithography. For instance, patterns can be formed from a photo resist (PR) layer by passing light energy through a mask (or reticle) having an arrangement to image the desired pattern onto the PR layer. As a result, the pattern is transferred to the PR layer. In areas where the PR is sufficiently exposed and after a development cycle, the PR material can become soluble such that it can be removed to selectively expose an underlying layer (e.g., a semiconductor layer, a metal or metal containing layer, a dielectric layer, etc.). Portions of the PR layer not exposed to a threshold amount of light energy will not be removed and serve to protect the underlying layer. The exposed portions of the underlying layer can then be etched (e.g., by using a chemical wet etch or a dry reactive ion etch (RIE)) such that the pattern formed from the PR layer is transferred to the underlying layer. Alternatively, the PR layer can be used to block dopant implantation into the protected portions of the underlying layer or to retard reaction of the protected portions of the underlying layer. Thereafter, the remaining portions of the PR layer can be stripped.
There is a pervasive trend in the art of IC fabrication to increase the density with which various structures are arranged. As a result, there is a corresponding need to increase the resolution capability of lithography systems. One promising alternative to conventional optical lithography is a next-generation lithography technique known as extreme ultraviolet (EUV) lithography where wavelengths in the range of about 11 nm to about 14 nm are used to expose the PR layer. For example, using a numerical aperture of about 0.25, a wavelength of about 13.4 nm and a k1 value of about 0.6, it has been proposed that a resolution of about 32 nm can be achieved.
However, attempts to implement EUV lithography have encountered a number of challenges. With additional reference to FIG. 1, a conventional EUV lithography mask 10 is illustrated. The mask includes a glass substrate 12. A multilayer reflector film stack 14 is deposited on an upper surface of the substrate 12. The multilayer stack 14 can be made from alternating layers of high-Z and low-Z materials, such as molybdenum and silicon layers (Mo/Si), molybdenum carbon and silicon layers (Mo2C/Si), molybdenum and beryllium layers (Mo/Be), or molybdenum ruthenium and beryllium layers (MoRu/Be). Together, the substrate 12 and multilayer stack 14 can form a mask blank. To function as an EUV lithography mask, absorbing material can be deposited and patterned on the multilayer stack 14 to form a plurality of absorbers 16. Although the absorbers 16 are illustrated as individual structures, the absorbers 16 can form an interconnected pattern. A buffer layer (not shown) can be formed between the multilayer stack 14 and the absorbing material 16 to facilitate etching of the absorbing material with minimal damage to the multilayer stack 14. Absorbers have been made from chromium (Cr), titanium nitride (TiN) and tantalum nitride (TaN). Alternatively, as shown in FIG. 2, a functional EUV lithography mask can be formed by patterning the multilayer stack 14 of the mask blank to form a plurality of individual or interconnected multilayer reflectors 14′. In this alternative arrangement, a conductive layer 18 can be present between the etched multilayer reflectors 14′ and the substrate 12.
The EUV light used to expose the wafer generates photoelectrons, thereby causing the top of the mask 10 (e.g., the absorbers 16 and multilayer stack 14) to become electrically charged. This condition can result in particle attraction and/or electrostatic discharge (ESD) damage to the mask 10, both of which can lead to image pattern defects. Unfortunately, attempts to ground the absorbers 16 and/or multilayer stack 14 using direct mechanical contact will also lead to particle attraction and image pattern defects.
Accordingly, there exists a need in the art for improved EUV lithography masks and methods of grounding EUV lithography masks.